1. Field of the Invention
The invention relates in general to simulation during design of integrated circuits and more particularly, to simulation to estimate integrated circuit substrate noise.
2. Description of the Related Art
FIG. 1 is an illustrative perspective view of a mixed-signal integrated circuit that includes a digital subsystem and an analog subsystem and that also includes a cross-section view of the IC substrate. The digital and analog subsystems are physically separated in different circuit blocks. Even though the digital and analog blocks of the integrated circuit (IC) may be separated by relatively large distances, they are nevertheless electrically coupled through a shared substrate. The substrate is a conductive medium vulnerable to a phenomenon called “substrate noise” or “substrate coupling”. Substrate noise can result in un-intended interaction between the digital and analog components of a chip through the underlying silicon substrate. Analog systems generally lack the degree of noise immunity of digital circuits, and the substrate coupling noise can degrade analog performance.
Digital circuits typically operate with two discrete voltages, one corresponding to logic 0 and another corresponding to logic 1. Usually, the logic 1 value is encoded as the power supply voltage (or VDD), and logic 0 is encoded as the ground voltage (or 0, or VSS) in CMOS digital chips. During circuit operation, the signals on the digital portion switch from logic 1 to logic 0 or vice versa. In other words, the voltage on the signal line changes from one extreme allowed voltage to the other.
Analog circuits usually operate with voltage values that represent continuous analog behavior rather than switch between discrete voltages. Analog circuit examples include oscillators, Analog-to-Digital and Digital-to-Analog converters, mixers, amplifiers. Analog circuits typically operate with signals that are significantly smaller in amplitude than digital signals. Analog circuits are, therefore, generally more sensitive to effects of substrate noise than are digital circuits.
Substrate noise can cause fluctuations in the voltage potential of the substrate, which can affect CMOS device behavior. For example, it can change the threshold voltage of a CMOS transistor. For a digital circuit, this could result in a small change in the delay of a logic gate. However, for an analog circuit, the effect can be much more severe. For instance, in an amplifier, a change in threshold voltage can change the operating point of the amplifier and significantly reduce the gain. In a filter, it can reduce the noise margin.
Digital circuit switching generates substrate noise through multiple mechanisms. For instance, digital circuit switching results in substrate noise injection to the substrate from the junction of a digitally switching transistor. Also, digital circuit switching results in substrate noise injection due to power supply fluctuations. More noise ordinarily will be injected to the substrate from areas of the IC with a higher density of digital transistors. The power supply rails of an IC are tied at periodic intervals to the substrate using electrical contacts. This ensures that the substrate is kept at a desired potential. Especially in the digital circuit blocks of the chip, significant current is drawn on the power supply rails, and the power supply voltage fluctuates as a function of the switching activity. This voltage fluctuation is transferred to the substrate through the electrical contacts, and gets propagated through the substrate, eventually reaching the analog circuit blocks of the chip. The variation in power supply voltages can be exacerbated by inductance of the power supply lines bringing power to the chip, as well as by on-chip inductances.
In a CMOS circuit, electrical contacts comprise n+ and p+ diffusion regions adjacent NMOS or PMOS devices that are used to set the bulk terminal of the device to either ground or VDD depending on device type. When a digital signal transition occurs, a spike of current from the power supply is used to charge the output load. A significant portion of the current is discharged to ground, which the substrate ultimately connects to. In general, noise injection from the power supply fluctuation is a more significant substrate noise source than noise injection from switching transistors.
These discharge currents work in tandem with the parasitics of the power and ground lines to cause ringing in the supplies. However, since the substrate is connected to power and ground through low resistance substrate contacts, any such noise that appears on the power and ground lines appears also directly in the substrate. Once the noise has been injected into the substrate, it can propagate throughout the substrate. Although noise may be attenuated by the resistance of the substrate, it still can reach all areas of the chip. Substrate voltage fluctuations that reach analog transistors can have a detrimental impact upon their operation as described above.
An objective of substrate noise analysis is to estimate the substrate noise at the substrate terminals of sensitive analog devices. This information can be used to predict whether an analog circuit will function properly in the presence of substrate noise. More commonly, the substrate noise estimate can be used to decide the relative goodness of different chip floorplan alternatives, and to decide upon a floorplan that is acceptable in view of the estimated impact of substrate noise upon analog circuit performance. Substrate noise estimation also can be used to guide power supply design; if more power supply pins and higher decoupling is provided, the power supply lines will have less fluctuation, leading to less substrate noise.
In the past, substrate noise analysis often involved identification of substrate noise sources from simulation of digital circuit switching. Identification of substrate noise sources through simulation was especially challenging since it required not only knowledge of digital switching activity, but also identification of the actual source and physical location of the noise injectors that cause noise. Identification of the noise sources and their locations using circuit simulation could be particularly difficult.
Also, in the past, substrate noise analysis typically involved detailed extraction of an equivalent model of the substrate including resistance and capacitance. To accurately develop the substrate model, the complex geometries of IC structures such as, wells, contacts, well taps, diffusions and trenches were extracted from a design in the form of an RC network. However, such a shape-based extraction requires detailed information from semiconductor process recipes. Since this information often is not available until later in the design flow, it often was impractical to do perform satisfactorily accurate shape based extraction earlier in the design process. Moreover, such detailed extraction can be quite expensive in terms of run time and memory requirements.
As a result, estimates of substrate noise not only could be expensive, but also could be less effectual earlier in the design process before the availability of accurate detailed information concerning the substrate.
Thus, there has been a need for improvements to IC substrate noise analysis, especially during early stages of the IC design process when there is incomplete substrate information. The present invention meets this need.